The present invention relates to a method of forming a columnar bump electrode for bonding, on an external connection pad provided on a semiconductor substrate.
A wire bonding (WB) method is generally known as a method for connecting a bonding pad on a semiconductor circuit chip (e.g. LSI chip) and a terminal on a print wiring board (PWB). According to the WB method, metal wires of Au, Cu, Al, etc. with a diameter of 25 to 30 .mu.m.phi. are used one by one in order to successively connect the bonding pads of the LSI chip and the connection terminals on the print wiring board by means of thermal compression bonding or ultrasonic bonding. The WB method is now most widely used as a connecting method.
However, the WB (wiring bonding) method has problems in that it cannot cope with recent development in integration density of semiconductor integrated circuits, an increase in number of pins due to higher operation speed, a decrease in pitch of bonding pads, or mounting of thinner semiconductor devices at higher density.
Under the circumstances, attention has been paid to a TAB (Tape Automated Bonding) method and an FCB (Flip Chip Bonding) method as methods of connecting LSI chips, which are capable of coping with gang bonding, a decrease in pitch of bonding pads, and mounting of thinner semiconductor devices at higher density. In particular, the FCB method, which requires a least mounting area, is adopted in manufacturing consumer products.
In the FCB method, electrodes called bumps are formed on bonding pads of LSI chips. There are two types of bumps: melt-type bumps formed of solder, etc. with a height of 80 to 150 .mu.m on bonding pads arranged at a bonding pad pitch of 150 to 250 .mu.m; and non-melt type bumps formed of Au, etc. with a height of 20 to 25 .mu.m on bonding pads arranged at a bonding pad pitch of 150 .mu.m or less.
In consideration of consumer products to be manufactured in the future, it is expected that non-melt type solder bumps will prevail over melt-type solder bumps since most of LSI chips have peripheral-type bonding pad array having a bonding pad pitch of 150 .mu.m or less according to WB specifications.
In the case of consumer products, organic boards are generally used. When an LSI chip is to be directly bonded to an organic substrate by the FCB (Flip Chip Bonding) method, a thermal stress due to a difference in thermal expansion coefficient between the print wiring board (PWB) and the LSI chip is entirely applied to the connection portions.
As a result, there is a problem with the reliability of the connection portions when conventional non-melt type bumps with a height of 20 to 25 .mu.m. In order to solve this problem, there is a method of increasing the height of the connection portion between the print wiring board and the LSI chip. In order to carry out this method, a bump electrode with a height of 30 .mu.m or more needs to be used. In the prior art, a bump electrode with a height of 30 .mu.m or more has been formed by two methods: a method of using a resist layer with a thickness of 30 .mu.m or less, which is adopted in forming an Au bump; and a method of using a resist layer of 30 .mu.m or more. The conventional bump electrode may be formed by the steps illustrated in FIGS. 13 to 17.
At first, as shown in FIG. 13, a bonding pad 2 formed of, e.g. aluminum is formed on a silicon substrate 1. A passivation layer 3 formed of silicon oxide or silicon nitride is provided so as to cover the surface of the substrate 1 and that portion of the upper surface of the bonding pad 2, which excludes a central portion of the upper surface of the bonding pad 2. The central portion of the bonding pad 2 is exposed through an opening portion 4.
Subsequently, as shown in FIG. 14, an under-bump metallurgy (UBM) layer 5 is formed on the entire upper surface of the resultant structure, and a resist layer 6 with a thickness of 1 to 30 .mu.m is formed. An opening portion 7 is formed in the resist layer 6 in a position corresponding to the bonding pad 2. A bump electrode 8 is formed to a height of, e.g. 60 .mu.m by means of electroplating, with the UBM layer 5 being used as a plating current path. Thus, the bump electrode 8, as shown in FIG. 14, is formed.
In the above-described method, the height of the bump is set at 60 .mu.m, and the thickness of the resist layer 6 is at 1 to 30 .mu.m. Thus, the bump electrode 8 has a horizontal growth portion from the resist opening portion 7 (i.e. a growth portion from the resist opening portion 7) at each side, which is 30 to 59 .mu.m long. Then, the resist layer 6 is removed and, with the bump electrode 8 used as a mask, an exposure portion of the UBM layer 5 is removed by a wet etching method or a dry etching method. Thus, a mushroom-shaped bump electrode 8 is obtained, as shown in FIG. 15.
In this method of forming the bump electrode, if the height of the bump electrode 8 is increased, the horizontal extension of thereof is also increased. Accordingly, in order to prevent a short-circuit between adjacent bump electrodes 8, it is necessary to increase a bonding pad pitch. As a result, it is difficult to decrease the bonding pad pitch. In order to solve this problem, there is a method of forming a bump electrode by using a thick resist. In this method, the bump electrode is formed by the steps illustrated in FIGS. 13, 16 and 17. The step illustrated in FIG. 13 has already been described.
As is shown in FIG. 16, a resist layer 9 comprising two resist films 9a and 9b or a single resist film (not shown) is formed. An opening portion 11 is formed in the resist layer 9 in a position corresponding to the bonding pad 2.
Subsequently, electroplating is performed, with the UBM layer 5 being used as a current path, thereby filling the inside of the opening portion 11 with gold, etc. Thus, a column bump electrode 12 is formed.
Then, the resist layer 9 is removed and, with the bump electrode 12 used as a mask, an exposure portion of the UBM layer 5 is etched away by a wet etching method or a dry etching method. Thus, the column bump electrode 12 with a height of 30 .mu.m or more is formed, as shown in FIG. 17.
In the above method, when the thick resist layer is formed of a liquid type resist, the limit value of the thickness thereof is 60 to 70 .mu.m in consideration of the current coating techniques and resist material characteristics. The distribution in film thickness indicates that the resist layer is formed in a concave lens shape. Consequently, the thickness of the resist layer is non-uniform, and uniform exposure cannot be achieved. For these reasons, the bump electrode cannot be formed with high accuracy. Moreover, the material of the resist is very expensive, and the efficiency of use of resist material is low. As a result, the cost for forming the bump electrode is high.
Furthermore, when a thick resist layer is obtained by multi-coating a plurality of thin liquid-type resists or by laminating a plurality of dry-type resists, the number of resist patterning steps increases double or more.
Besides, the alignment between the silicon substrate and a mask, with the resist layer having a thickness of 30 .mu.m or more interposed, becomes more difficult as the thickness of the resist increases. In a worst case, the alignment becomes impossible. This problem is peculiar to the thick resist layer.